M16C65 Datasheet, PDF (292/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
15. Watchdog Timer
VW2C3 (WDT Detection Flag) (b3)
Use this bit in an interrupt routine to determine the source of the interrupts from the watchdog timer, the
oscillation stop/re-oscillation detection, the voltage monitor 1, and the voltage monitor 2.
Conditions to become 0:
• Hardware reset, power-on reset, or voltage monitor 0 reset
• Writing 0 by a program
Condition to become 1:
• Watchdog timer underflow detected
(This flag remains unchanged even if 1 is written by a program.)
15.2.2 Count Source Protection Mode Register (CSPR)
Count Source Protection Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0000000
Symbol
CSPR
Address
037Ch
After Reset
0000 0000b
(When the CSPROINT bit in the OFS1 address is 1)
1000 0000b
(When the CSPROINT bit in the OFS1 address is 0)
Bit Symbol
Bit Name
Function
RW
—
(b6-b0)
Reserved bits
Set to 0
RW
CSPRO
Count source protection mode
select bit
0 : Count source protection mode
disabled
1 : Count source protection mode enabled
RW
CSPRO (Count Source Protection Mode Select Bit) (b7)
Select the CSPRO bit before the watchdog timer starts counting. Once counting starts, do not change
the CSPRO bit.
Condition to become 0:
• Reset when the CSPROINI bit in the OFS1 address is 1.
(This flag remains unchanged even if 0 is written by a program.)
Condition to become 1:
• When the CSPROINI bit in the OFS1 address is 0
• Write 0, and then write 1.
Make sure no interrupts or DMA transfers will occur between setting the bit to 0 and setting it to 1.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 257 of 791