M16C65 Datasheet, PDF (21/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

23.2.11 UARTi Special Mode Register 2 (UiSMR2) (i = 0 to 2, 5 to 7) .................. 505
23.2.12 UARTi Special Mode Register 3 (UiSMR3) (i = 0 to 2, 5 to 7) .................. 506
23.2.13 UARTi Special Mode Register 4 (UiSMR4) (i = 0 to 2, 5 to 7) .................. 507
23.3 Operations....................................................................................................... 508
23.3.1 Clock Synchronous Serial I/O Mode......................................................... 508
23.3.2 Clock Asynchronous Serial I/O (UART) Mode.......................................... 517
23.3.3 Special Mode 1 (I²C mode) ...................................................................... 527
23.3.4 Special Mode 2 ......................................................................................... 537
23.3.5 Special Mode 3 (IE mode) ........................................................................ 542
23.3.6 Special Mode 4 (SIM Mode) (UART2) ...................................................... 544
23.4 Interrupts ......................................................................................................... 549
23.4.1 Interrupt Related Registers....................................................................... 549
23.4.2 Reception Interrupt ................................................................................... 550
23.5 Notes on Serial Interface UARTi (i = 0 to 2, 5 to 7) ......................................... 551
23.5.1 Clock Synchronous Serial I/O................................................................... 551
23.5.2 UART (Clock Asynchronous Serial I/O) Mode.......................................... 553
23.5.3 Special Mode 1 (I2C Mode) ...................................................................... 553
23.5.4 Special Mode 4 (SIM Mode) ..................................................................... 553
24. Serial Interface SI/O3 and SI/O4.......................................................... 554
24.1 Introduction...................................................................................................... 554
24.2 Registers ......................................................................................................... 556
24.2.1 Peripheral Clock Select Register (PCLKR) .............................................. 557
24.2.2 SI/O Transmit/Receive Register (SiTRR) (i = 3, 4) .................................. 557
24.2.3 SI/Oi Control Register (SiC) (i = 3, 4) ...................................................... 558
24.2.4 SI/Oi Bit Rate Register (SiBRG) (i = 3, 4) ................................................ 559
24.2.5 SI/O3, 4 Control Register 2 (S34C2) ........................................................ 559
24.3 Operations....................................................................................................... 560
24.3.1 Basic Operations ...................................................................................... 560
24.3.2 CLK Polarity Selection.............................................................................. 560
24.3.3 LSB First or MSB First Selection .............................................................. 561
24.3.4 Internal Clock............................................................................................ 562
24.3.5 Function for Selecting SOUTi State after Transmission............................ 563
24.3.6 External Clock .......................................................................................... 564
24.3.7 SOUTi Pin................................................................................................. 564
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