M16C65 Datasheet, PDF (526/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
RXDi
RXD data
reverse circuit
IOPOL
No reverse
0
1
Reverse
STPS
1SP
0
SP
SP
1
2SP
PRYE
PAR
disabled
0
PAR
1
PAR enabled
I²C
clock sync
type
0
1
UART
SMD2 to SMD0
Clock sync type
UART
(7 bits)
UART
(8 bits)
0
UART (7 bits)
0
1
I²C
UART
(9 bits)
1
I²C
clock sync type
UART
(8 bits)
UART
(9 bits)
UARTi receive register
0 0 0 0 0 0 0 D8
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiRB
register
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB / LSB conversion circuit
D7
D6
D5
D4
D3
D2
D1
D0
UiTB
register
STPS
2SP
1
SP
SP
0
1SP
SP : Stop bit
PAR: Parity bit
i = 0 to 2, 5 to 7
PRYE _{SMD2 to SMD0}
PAR enabled _UART
1
1
PAR
0
PAR
disabled
0
I²C
clock sync
type
I²C
UART
(9 bits)
1
UART
(8 bits)
UART
(9 bits)
I²C
clock sync type
1
0
UART
(7 bits)
UART
(8 bits)
Clock sync type
0
UART (7 bits)
UARTi transmit register
Error signal output disabled ^IOPOL No reverse
0
0
UiERE 1
Error signal
output
circuit
Error signal output enabled
1
Reverse
TXD data
reverse
circuit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bits in the UiMR register
CLK1 to CLK0, CKPOL, CRD, CRS
: Bits in the UiC0 register
UiERE
: Bit in the UiC1 register
Figure 23.4 UARTi Transmit/Receive Unit Block Diagram
TXDi
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 491 of 791