M16C65 Datasheet, PDF (207/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
11. Bus
11.3.5.7 HOLD Signal
This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When
input to the HOLD pin is pulled low, the bus is placed in a hold state after the current bus access is
completed. While the HOLD pin is held low, the bus remains in a hold state. When the bus is in a hold
state, the HLDA pin outputs a low-level signal.
Table 11.8 shows the Pin Status in Hold State Caused by the HOLD Input.
Table 11.8 Pin Status in Hold State Caused by the HOLD Input
Item
BCLK
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL,WRH,
WR, BHE
I/O ports
P0, P1, P3, P4 ⁽¹⁾
HLDA
P6 to P14
ALE
Note:
1. When I/O port function is selected.
Output
High-impedance
Status
High-impedance
Maintains status when HOLD signal is received
Low-level output
Undefined
11.3.5.8 BCLK Output
When the PM07 bit in the PM0 register is set to 0 (output enabled), a clock with the same frequency
as the CPU clock is output as BCLK from the BCLK pin. Refer to 8.4 “CPU Clock and Peripheral
Function Clocks”.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 172 of 791