M16C65 Datasheet, PDF (489/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
22. Remote Control Signal Receiver
DRFLG (Data Receiving Flag) (b2)
The DRFLG bit indicates the receiving state of the remote control signal.
Condition to become 0:
• The counter value is larger than values of registers PMCiHDPMAX, PMCiD0PMAX, and
PMCiD1PMAX (if the counter value is larger than these register values, this bit becomes 0 after
waiting for 1 to 2 cycles of the count source).
Condition to become 1:
It depends on bits TYP1 to TYP0 in the PMCiCON1 register (receive mode select).
• When bits TYP1 to TYP0 are 00b (pulse period measurement) or 01b (high level width
measurement):
rising edge of the PMCi internal input signal
• When bits TYP1 to TYP0 are 10b (pulse width measurement):
rising edge and falling edge of the PMCi internal input signal
BFULFLG (Receive Buffer Full Flag) (b3)
Condition to become 0:
• The value of the PMC0RBIT register changes from 48 to 1.
Condition to become 1:
• The value of the PMC0RBIT register is 48.
PTHDFLG (Header Pattern Match Flag) (b4),
PTD0FLG (Data 0 Pattern Match Flag) (b5),
PTD1FLG (Data 1 Pattern Match Flag) (b6),
SDFLG (Special Pattern Match Flag) (b7)
Condition to become 0:
• The EN bit is 0 (PMCi stops)
• DRFLG bit in the PMCiSTS register changes from 0 to 1 (next frame reception starts)
• Refer to Table 22.6 “Measurements and Flag”.
Condition to become 1:
• Refer to Table 22.6 “Measurements and Flag”.
Table 22.6 Measurements and Flag
Value (Measurements) of the PMCiTIM Register
Flag
PTHDFLG PTD0FLG PTD1FLG
SDFLG
Between PMCiHDPMIN and PMCiHDPMAX
(header measurement in PMCi)
1
0
0
0
Between PMCiD0PMIN and PMCiD0PMAX
0
1 ⁽¹⁾
0
0
Between PMCiD1PMIN and PMCiD1PMAX
0
0
1 ⁽¹⁾
0
Between PMCiHDPMIN and PMCiHDPMAX
(special data measurement in PMCi)
0
0
0
1 ⁽¹⁾
Other than those above
0
0
0
0
Note:
1. When the HDEN bit in the PMCiCON0 register is 1(header enabled), PTD0FLG, PTD1FLG, and
SDFLG remain unchanged until header is detected.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 454 of 791