M16C65 Datasheet, PDF (345/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
17. Timer A
TAiIN input
FFFFh
Count operations
n ^{Count start}
Overflow
reload
Decrement
0000h
TAiS bit
in TABSR register
TAiUD bit
in UDF register
TAiOUT output
POFSi = 0
POFSi = 1
Increment
n+1
Underflow
reload
FFFFh-n+1
Low-level output
at count stop
High-level output
at count stop
Output reversed at underflow or overflow
Count stop
Low-level output at count stop
High-level output at count stop
IR bit
in TAiIC register
Set to 0 by an interrupt request acknowledgement or by a program.
i = 0 to 4
POFSi: Bits in the TAPOFS register
The above timing diagram applies when the register bits are set as follows:
- Bits TAiTGH to TAiTGL in the ONSF or TRGSR register = 00b
- The MR1 bit in the TAiMR register
=0
- The MR0 bit in the TAiMR register
= 1 (pulse output)
- The TCK0 bit in the TAiMR register
= 0 (reload type)
(The falling edge of the TAiIN pin input is counted.)
Figure 17.6 Operation Example in Event Counter Mode
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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