M16C65 Datasheet, PDF (583/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.6.2 Format
Two formats are available: direct format and inverse format.
For direct format, set the PRYE bit in the U2MR register to 1 (parity enabled), the PRY bit to 1 (even
parity), the UFORM bit in the U2C0 register to 0 (LSB first) and the U2LCH bit in the U2C1 register to
0 (not inverted). When data is transmitted, the contents of the U2TB register are transmitted with the
even-numbered parity, starting from D0. When data is received, the receive data are stored in the
U2RB register, starting from D0. The even-numbered parity is used to determine when a parity error
occurs.
For inverse format, set the PRYE bit to 1, the PRY bit to 0 (odd parity), the UFORM bit to 1 (MSB
first), and the U2LCH bit to 1 (inverted). When data is transmitted, the contents of the U2TB register
are logically inverted and are transmitted with odd-numbered parity, starting from D7. When data is
received, the receive data is logically inverted and stored in the U2RB register, starting from D7. The
odd-numbered parity is used to determine when a parity error occurs.
Figure 23.30 shows SIM Interface Format.
(1) Direct format
High
Transmit/receive clock
Low
TXD2 ^High
Low
(2) Inverse format
High
Transmit/receive clock
Low
TXD2 ^High
Low
Figure 23.30 SIM Interface Format
D0 D1 D2 D3 D4 D5 D6 D7 P
P : Even parity
D7 D6 D5 D4 D3 D2 D1 D0 P
P : Odd parity
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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