M16C65 Datasheet, PDF (597/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
24. Serial Interface SI/O3 and SI/O4
24.3.4 Internal Clock
When the SMi6 bit in the SiC register is 1, data is transmitted/received using internal clock. The internal
clock is selected by the SM22 bit in the S32C2 register, the PCLK1 bit in the PLCKR register, and bits
SMi1 to SMi0 in the SiC register. When the internal clock is used as transmit/receive clock, the SOUTi
pin becomes high-impedance from when the SMi3 bit in the SiC register is set to 1 (SI/Oi enabled) and
the SMi2 bit is set to 0 (SOUTi output enabled) to when the first data is output.
When writing the transmit data into the SiTRR register, data transmission/reception starts by outputting
the transmit/receive clock from the CLKi pin after waiting for 0.5 to 1.0 cycles of the transmit/receive
clock. When completing the transmission/reception of 8 bits data, the transmit/receive clock from the
CLKi pin stops.
Figure 24.4 shows SI/Oi Operation Timing (Internal Clock).
Si/Oi internal clock
CLKi output
Write signal to the
SiTRR register
SOUTi output
SINi input
Transmission/reception starts after waiting for 0.5 to 1.0 cycles of transmit/receive clock by writing into the SiTRR register.
Hi-Z
Hi-Z
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
IR bit in the SiIC
register
i = 3, 4
The above diagram applies under the following conditions:
In the SiC register, SMi2 = 0 (SOUTi output), SMi3 = 1 (SOUTi output, CLKi function), SMi4 = 0 (transmit data is output at
falling edge of transmist/receive clock and receive data is input at rising edge), SMi5 = 0 (LSB first), SMi6 = 1 (internal
clock).
In the S34C2 register, the SM26 bit (SOUT3) or SM27 bit (SOUT4) = 0 (high-impedance after transmission).
Figure 24.4 SI/Oi Operation Timing (Internal Clock)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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