M16C65 Datasheet, PDF (745/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
30. Flash Memory
30.8.1 Operating Speed
Set a CPU clock frequency of 10 MHz or less by the CM06 bit in the CM0 register and bits CM17 and
CM16 in the CM1 register before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17
bit in the PM1 register to 1 (wait state).
30.8.2 Data Protect Function
Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02
bit to 0 (lock bit enabled). The lock bit allows blocks to be individually protected (locked) against
programming and erasure. This prevents data from being inadvertently written to or erased from the
flash memory. Table 30.11 lists Lock Bit and Block State.
Table 30.11 Lock Bit and Block State
FMR02 Bit
in the FMR0 Register
0 (enabled)
1 (disabled)
Lock Bit
0 (locked)
1 (unlocked)
0 (locked)
1 (unlocked)
Block State
Protected against programming and erasure
Can be programmed or erased
Can be programmed or erased
Condition to become 0:
• Execute the lock bit command
Condition to become 1:
• Execute the block erase command while the FMR02 bit in the FMR0 register is set to 1 (lock bit
disabled).
If the block erase command is executed while the FMR02 bit is set to 1, the target block is erased
regardless of lock bit status. The lock bit data can be read by the read lock bit status command.
Refer to 30.8.4 “Software Command”, for details on each command.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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