M16C65 Datasheet, PDF (13/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

12.2.1 Data Bank Register (DBR) ....................................................................... 183
12.3 Operations....................................................................................................... 184
12.3.1 1-Mbyte Mode........................................................................................... 184
12.3.2 4-Mbyte Mode........................................................................................... 186
13. Programmable I/O Ports....................................................................... 192
13.1 Introduction...................................................................................................... 192
13.2 I/O Ports and Pins ........................................................................................... 194
13.3 Registers ......................................................................................................... 204
13.3.1 Pull-Up Control Register 0 (PUR0)........................................................... 205
13.3.2 Pull-Up Control Register 1 (PUR1)........................................................... 206
13.3.3 Pull-Up Control Register 2 (PUR2)........................................................... 207
13.3.4 Pull-Up Control Register 3 (PUR3)........................................................... 208
13.3.5 Port Control Register (PCR) ..................................................................... 209
13.3.6 Port Pi Registers (Pi) (i = 0 to 14)
............................................... 210
13.3.7 Port Pi Direction Registers (PDi) (i = 0 to 14)
............................. 212
13.3.8 NMI/SD Digital Filter Register (NMIDF).................................................... 213
13.4 Peripheral Function I/O ................................................................................... 214
13.4.1 Peripheral Function I/O and Port Direction Bits........................................ 214
13.4.2 Priority Level of Peripheral Function I/O................................................... 214
13.4.3 NMI/SD Digital Filter ................................................................................. 215
13.4.4 CNVSS ..................................................................................................... 215
13.5 Unassigned Pin Handling ................................................................................ 216
13.6 Notes on Programmable I/O Ports .................................................................. 218
13.6.1 Influence of the SD Input .......................................................................... 218
13.6.2 Influence of SI/O3 and SI/O4.................................................................... 218
13.6.3 100-Pin Package ...................................................................................... 218
13.6.4 80-Pin Package ........................................................................................ 218
14. Interrupts .............................................................................................. 219
14.1 Introduction...................................................................................................... 219
14.2 Registers ......................................................................................................... 220
14.2.1 Processor Mode Register 2 (PM2) ........................................................... 222
A-6