M16C65 Datasheet, PDF (314/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
16. DMAC
16.3.6 Repeat Transfer Mode
In repeat transfer mode, when the DMAi transfer counter underflows, it is reloaded with the value of the
DMAi transfer counter reload register and DMA transfer continues. Figure 16.4 shows Operation
Example in Repeat Transfer Mode.
Repeat Transfer Mode
Bus
CPU
DMA
CPU
DMA
CPU
DMA
CPU
DMA
CPU
DMAS bit
When a transfer begins, the DMAS bit is set to 0.
Underflow
TCRi bit Undefined 02h
01h
Reload
IR bit
00h
02h
01h
Set to 0 by an interrupt request acknowledgement
or by a program.
DMAE bit
Set to 1 by a program.
i = 0 to 3
DMAS, DMAE : Bits in the DMiCON register
IR : Bit in the DMiIC register
The above diagram applies when the register bit is set as follows:
Value in the TCRi register = 02h (there are three transfers).
Figure 16.4 Operation Example in Repeat Transfer Mode
16.3.7 Channel Priority and DMA Transfer Timing
If multiple channels among DMA0 to DMA3 are enabled and DMA transfer request signals are detected
active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the
DMAS bit on each channel is set to 1 (DMA requested) at the same time. In this case, the DMA
requests are arbitrated according to the following channel priority: DMA0 > DMA1 > DMA2 > DMA3.
The DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period
is described below. Figure 16.5 shows an example of DMA Transfer by External Sources.
In Figure 16.5, DMA0, which has a high channel priority, is received first to start a transfer when DMA0
and DMA1 requests are generated simultaneously. After one DMA0 transfer is completed, the bus
access privilege is returned to the CPU. When the CPU has completed one bus access, a DMA1
transfer starts. After one DMA1 transfer is completed, the bus access privilege is again returned to the
CPU.
In addition, DMA requests cannot be incremented since each channel has one DMAS bit. Therefore,
when DMA requests, such as DMA1 in Figure 16.5, occur more than once, the DMAS bit is set to 0
after receiving the bus access privilege. The bus access privilege is returned to the CPU when one
transfer is completed.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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