M16C65 Datasheet, PDF (198/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
11.2.3 External Area Wait Control Expansion Register (EWC)
11. Bus
External Area Wait Control Extension Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
EWC
Address
0011h
After Reset
00h
Bit Symbol
Bit Name
Function
RW
EWC00
b1 b0
0 0:2φ+3φ
RW
CS0 area wait extention bit
0 1:2φ+4φ
1 0:3φ+4φ
EWC01
1 1:4φ+5φ
RW
EWC10
b3 b2
0 0:2φ+3φ
RW
CS1 area wait extention bit
0 1:2φ+4φ
1 0:3φ+4φ
EWC11
1 1:4φ+5φ
RW
EWC20
b5 b4
0 0:2φ+3φ
RW
CS2 area wait extention bit
0 1:2φ+4φ
1 0:3φ+4φ
EWC21
1 1:4φ+5φ
RW
EWC30
b7 b6
0 0:2φ+3φ
RW
CS3 area wait extention bit
0 1:2φ+4φ
1 0:3φ+4φ
EWC31
1 1:4φ+5φ
RW
This register can be used as a separate bus area. When bits CSEi1W and CSEi0W in the CSE register
are 11b (select wait states by bits EWCi1 to EWCi0), bits EWCi1 to EWCi0 are enabled. (i = 0 to 3)
The number of cycles is as follows.
Example: 2φ + 3φ
The number of cycles between the falling edge and the rising edge of the RD or WR signal
The number of cycles between bus access start and the falling edge of the RD or WR signal
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 163 of 791