M16C65 Datasheet, PDF (104/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
6. Resets
6.4.3 Power-On Reset Function
When the RESET pin is connected to the VCC1 pin via a pull-up resistor, and the VCC1 pin voltage
level rises while the rise gradient is trth or more, the power-on reset function is enabled and the MCU
resets its pins, CPU, and SFRs. Also, when a capacitor is connected to the RESET pin, always keep
the voltage to the RESET pin 0.8 VCC or more.
When the input voltage to the VCC1 pin reaches the Vdet0 level or above, the fOCO-S starts counting.
When the fOCO-S count reaches 32, the internal reset signal is held high and the MCU executes the
program at the address indicated by the reset vector. The fOCO-S divided by 8 is automatically
selected as the CPU clock after reset.
The CWR bit in the RSTFR register becomes 0 (cold start-up) after power-on reset. Refer to 4. “Special
Function Registers (SFRs)” for the remaining SFR states after reset.
The internal RAM is not reset.
Use the voltage monitor 0 reset together with the power-on reset. Set the LVDAS bit in the OFS1
address to 0 (voltage monitor 0 reset enabled after hardware reset) to use the power-on reset. In this
case, the voltage monitor 0 reset is enabled (the VW0C0 bit and bit 6 in the VW0C register are 1 and
the VC25 bit in the VCR2 register is 1). Do not set these bits to 0 by a program.
Refer to 7. “Voltage Detector” for details of the voltage monitor 0 reset.
Figure 6.5 shows Example of Power-On Reset Circuit and Operation.
4.7 kΩ
(reference)
VCC
RESET
Vdet0
External
power VCC
Vpor1
trth
tw(por1)
Sampling clock
of digital filter
×
4
cycles
Vdet0
trth
Vpor2
Internal
reset signal
(low active)
1
fOCO-S
× 32
Power-on reset function
1
fOCO-S
× 32
Voltage monitor 0 reset
Figure 6.5 Example of Power-On Reset Circuit and Operation
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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