M16C65 Datasheet, PDF (572/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.4 Special Mode 2
Special mode 2 supports serial communication between one or multiple master devices and multiple
slaves devices. The transmit/receive clock polarity and phase are selectable. Table 23.20 lists the
Special Mode 2 Specifications.
Table 23.20 Special Mode 2 Specifications
Item
Specification
Data format
Transmit/receive clock
Character data length: 8 bits
• Master mode
The CKDIR bit in the UiMR register = 0 (internal clock):
-₂---₍---_n---^f-₊-^j----₁-----_{) fj = f1SIO, f2SIO, f8SIO, f32SIO}
n: Setting value of UiBRG register 00h to FFh
• Slave mode
The CKDIR bit = 1 (external clock selected): Input from the CLKi pin
Transmit/receive control
Controlled by input/output ports
Transmission start Conditions _{To start transmission, satisfy the following requirements.} ⁽¹⁾
• The TE bit in the UiC1 register
= 1 (transmission enabled)
• The TI bit in the UiC1 register
= 0 (data present in UiTB register)
Reception start Conditions
To start reception, satisfy the following requirements. ⁽¹⁾
• The RE bit in the UiC1 register
= 1 (reception enabled)
• The TE bit
= 1 (transmission enabled)
• The TI bit
= 0 (data present in the UiTB register)
Interrupt request generation
timing
Transmit interrupt: One of the following can be selected.
• The UiIRS bit in the UiC1 register= 0 (transmit buffer empty): When transferring
data from the UiTB register to the UARTi transmit register (at start of transmission)
• The UiIRS bit
=1 (transmission completed):
When the serial interface completed sending data from the UARTi transmit register
Receive interrupt:
• When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
Overrun error ⁽²⁾
This error occurs if the serial interface starts receiving the next unit of data before
reading the UiRB register and receives the 7th bit of the next unit of data.
Selectable functions
• CLK polarity selection
Data input/output can be chosen to occur synchronously with the rising or the falling
edge of the transmit/receive clock.
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected.
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register.
• Switching serial data logic
This function reverses the logic value of the transmit/receive data.
• Clock phase setting
Selectable from four combinations of transmit/receive clock polarities and phases
i = 0 to 2, 5 to 7
Notes:
1. When an external clock is selected, either of the following conditions must be met. If the CKPOL bit in the
UiC0 register is 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of
the transmit/receive clock), the external clock is in high state; if the CKPOL bit is 1 (transmit data output at
the rising edge and the receive data taken in at the falling edge of the transmit/receive clock), the external
clock is in low state.
2. If an overrun error occurs, the received data of the UiRB register will be undefined. The IR bit in the SiRIC
register remains unchanged.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 537 of 791