M16C65 Datasheet, PDF (68/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
2. Central Processing Unit (CPU)
2.2 Address Registers (A0 and A1)
A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic and
logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
The FB is a 16-bit register that is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
The INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.
2.5 Program Counter (PC)
The PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP are each comprised of 16 bits. The U flag is used to switch
between USP and ISP.
2.7 Static Base Register (SB)
The SB is a 16-bit register used for SB-relative addressing.
2.8 Flag Register (FLG)
The FLG is an 11-bit register that indicates the CPU state.
2.8.1 Carry Flag (C Flag)
The C flag retains a carry, borrow, or shift-out bit generated by the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z Flag)
The Z flag becomes 1 when an arithmetic operation results in 0. Otherwise it becomes 0.
2.8.4 Sign Flag (S Flag)
The S flag is set to 1 when an arithmetic operation results in a negative value. Otherwise it is set to 0.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when the B flag is set to 0. Register bank 1 is selected when this flag is set
to 1.
2.8.6 Overflow Flag (O Flag)
The O flag is set to 1 when an arithmetic operation results in an overflow. Otherwise it is set to 0.
2.8.7 Interrupt Enable Flag (I Flag)
The I flag enables maskable interrupts.
Maskable interrupts are disabled when the I flag is set to 0, and enabled when it is set to 1. The I flag is
set to 0 when an interrupt request is acknowledged.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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