M16C65 Datasheet, PDF (538/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.2.9 UART Transmit/Receive Control Register 2 (UCON)
UART Transmit/Receive Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
0250h
After Reset
X000 0000b
Bit symbol
Bit Name
Function
RW
U0IRS
UART0 transmit interrupt
source select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
RW
U1IRS
UART1 transmit interrupt
source select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
RW
U0RRM
UART0 continuous receive
mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
U1RRM
UART1 continuous receive
mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
Valid when CLKMD1 is 1
CLKMD0 UART1CLK, CLKS select bit 0 0 : Clock output from CLK1
RW
1 : Clock output from CLKS1
0 : CLK output is only from CLK1
CLKMD1 UART1CLK, CLKS select bit 1 1 : Transmit/receive clock output from
RW
multiple-pin output function selected
RCSP
Separate UART0
CTS/RTS bit
0 : CTS/RTS shared pin
1 : CTS/RTS separated
RW
—
(b7)
No register bit. If necessary, set to 0. Read as undefined value
—
Bits UiIRS and UiRRM of UART2 and UART5 to UART7 are bits in the UiC1 register.
CLKMD1 (UART1CLK, CLKS Select Bit 1) (b5)
When using multiple transmit/receive clock output pins, make sure the following condition is met:
the CKDIR bit in the U1MR register = 0 (internal clock)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 503 of 791