M16C65 Datasheet, PDF (558/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
23.3.2.2 Transmit/Receive Register Initialization
When the transmit/receive register needs to be initialized due to an interrupted transmission/
reception, follow the procedures below.
• Initializing the UiRB register (i = 0 to 2, 5 to 7)
(1) Set the RE bit in the UiC1 register to 0 (reception disabled).
(2) Set the RE bit in the UiC1 register to 1 (reception enabled).
• Initializing the UiTB register
(1) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled).
(2) Reset bits SMD2 to SMD0 in the UiMR register to 001b, 101b, and 110b.
(3) Set 1 (transmission enabled), regardless of the set value of the TE bit in the UiC1 register.
23.3.2.3 LSB First/MSB First Select Function
As shown in Figure 23.14, the bit order can be selected by using the UFORM bit in the UiC0 register.
This function is valid when the character bit length is 8 bits.
(1) UFORM bit in the UiC0 register = 0 (LSB first)
CLKi
TXDi
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RXDi
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) UFORM bit in the UiC0 register = 1 (MSB first)
CLKi
TXDi
ST D7 D6 D5 D4 D3 D2 D1 D0 P SP
RXDi
ST D7 D6 D5 D4 D3 D2 D1 D0 P SP
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2, 5 to 7
The above applies under the following conditions.
- The CKPOL bit in the UiC0 register is 0 (transmit data output at the falling edge and the
receive data taken in at the rising edge of the transmit/receive clock).
- The UiLCH bit in the UiC1 register is 0 (no reverse).
- The STPS bit in the UiMR register is 0 (1 stop bit).
- The PRYE bit in the UiMR register is 1 (parity enabled).
Figure 23.14 Bit Order
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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