M16C65 Datasheet, PDF (259/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
14.2.3 Interrupt Control Register 2 (INT7IC, INT6IC,
INT3IC, S4IC/INT5IC, S3IC/INT4IC, INT0IC to INT2IC)
14. Interrupts
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INT7IC
INT6IC
INT3IC
S4IC/INT5IC
S3IC/INT4IC
INT0IC to INT2IC
Address
0042h
0043h
0044h
0048h
0049h
005Dh to 005Fh
After Reset
XX00 X000b
XX00 X000b
XX00 X000b
XX00 X000b
XX00 X000b
XX00 X000b
Bit Symbol
Bit Name
Function
ILVL0
ILVL1
ILVL2
IR
Interrupt priority level select
bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Interrupt request bit
0: Interrupt not requested
1: Interrupt requested
POL Polarity select bit
0 : Select falling edge
1 : Select rising edge
—
(b5)
Reserved bit
Set to 0
—
(b7-b6)
No register bits. If necessary, set to 0. Read as undefined value
RW
RW
RW
RW
RW ⁽¹⁾
RW
RW
—
Rewrite this register at a point that does not generate an interrupt request.
When multiple interrupt sources share the register, select an interrupt source in the IFSR register.
ILVL2-ILVL0 (Interrupt Priority Level Select Bit) (b2-b0)
In memory expansion or microprocessor mode, set bits ILVL2 to ILVL0 in registers INT6IC and INT7IC
to 000b (interrupts disabled).
When the BYTE pin is low in memory expansion or microprocessor mode, set bits ILVL2 to ILVL0 in
registers INT3IC, INT4IC, and INT5IC to 000b (interrupts disabled).
IR (Interrupt Request Bit) (b3)
The IR bit can only be set to 0 (do not write 1).
POL (Polarity Select Bit) (b4)
When the IFSRi bit in the IFSR register is 1 (both edges), set the POL bit in the INTiIC register to 0
(falling edge) (i = 0 to 5). Similarly, when bits IFSR30 and IFSR31 in the IFSR3A register are 1 (both
edges), set the POL bit in registers INT6IC and INT7IC to 0 (falling edge).
Set the POL bit in the S3IC or S4IC register to 0 (falling edge) when the IFSR6 bit in the IFSR register
is 0 (SI/O3 selected) or IFSR7 bit is 0 (SI/O4 selected), respectively.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 224 of 791