M16C65 Datasheet, PDF (223/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
12. Memory Space Expansion Function
In the example below, the CS pin of a 4-Mbyte ROM is connected to the MCU’s CS0 pin. The 4-Mbyte
ROM address input pins AD21, AD20, and AD19 are connected to the MCU’s CS3, CS2, and CS1 pins,
respectively. The address input AD18 pin is connected to the MCU’s A19 pin. Figure 12.6 to Figure 12.8
show the relationship of addresses between the 4-Mbyte ROM and the MCU in the connection example
of Figure 12.5.
In microprocessor mode or memory expansion mode, where the PM13 bit in the PM1 register is 0,
banks are located every 512 Kbytes. Setting the OFS bit in the DBR register to 1 (offset) allows the
accessed address to be offset by 40000h, allowing even data overlapping at a bank boundary to be
accessed in succession.
In memory expansion mode, where the PM13 bit is 1, each 512-Kbyte bank can be accessed in 256
Kbyte units by switching them with the OFS bit.
Because the SRAM can be accessed when the chip select signals S2 is high and S1 is low, CS0 and
CS2 can be connected to S2 and S1, respectively. If SRAM does not have the input pins that accept
high active and low active chip select signals (S1, S2), CS0 and CS2 should be decoded externally to
the chip.
D0 to D7
A0 to A16
A17
A19
8
DQ0 to DQ7
17
AD0 to AD16
AD17
AD18
CS1
AD19
CS2
AD20
CS3
AD21
RD
OE
CS0
CS
Note :
WR
DQ0 to
DQ7
AD0 to
AD16
OE
S2
S1 ⁽¹⁾
W
1. If only one chip select pin (S1 or S2) is present, an external circuit must be used for decoding.
Figure 12.5 External Memory Connection Example in 4-Mbyte Mode
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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