M16C65 Datasheet, PDF (215/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
11. Bus
BCLK
Address
CSi
Read data
RD
Write data
WR, WRL, WRH
Recovery cycle
A
← Address is held
(1)
RD
WD
← Data is held
i = 0 to 3
A: Address
RD: Read data (input) WD: Write data (output)
Note:
1. When consecutively accessing to the same chip-select area, CSi keeps outputting a low level.
The above diagram shows a case under the following conditions:
- Bits EWR1 and EWR0 in the EWR register are 01b (one recovery cycle inserted).
- The CSiW bit in the CSR register is 0 (wait state).
- Bits CSEi1W and CSEi0W in the CSE register are 11b (select a bus cycle pattern by the EWC register ).
- Bits EWCi1 and EWCi0 in the EWC register are 00b (2 φ + 3 φ).
Figure 11.10 Recovery Cycle
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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