M16C65 Datasheet, PDF (277/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
14. Interrupts
14.7.5 Saving Registers
In the interrupt sequence, the FLG register and PC are saved on the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG
register, 16 bits in total, are saved on the stack first. Next, the 16 low-order bits of the PC are saved.
Figure 14.5 shows the Stack Status Before and After Acceptance of Interrupt Request.
The other necessary registers must be saved by a program at the beginning of the interrupt routine.
Use the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address
Stack
MSB
LSB
Address
Stack
MSB
LSB
m-4
m-3
m-2
m-1
m
Contents of previous stack
m + 1 ^{Contents of previous stack}
[SP]
SP value before
interrupt request is accepted.
m-4
m-3
m-2
PCL
PCM
FLGL
m-1
FLGH
PCH
m
Contents of previous stack
m + 1 Contents of previous stack
[SP]
New SP value
PCL : 8 low-order bits of PC
PCM : 8 middle-order bits of PC
PCH : 4 high-order bits of PC
FLGL : 8 low-order bits of FLG
FLGH : 4 high-order bits of FLG
Stack status
before interrupt request is acknowledged
Stack status
after interrupt request is acknowledged
Figure 14.5 Stack Status Before and After Acceptance of Interrupt Request
The register save operation carried out in the interrupt sequence is dependent on whether the SP ⁽¹⁾, at
the time of acceptance of an interrupt request, is even or odd. If the SP ⁽¹⁾ is even, the FLG register and
the PC are saved 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 14.6
shows the Register Save Operation.
Note:
1. When an INT instruction with software numbers 32 to 63 has been executed, it is the SP
indicated by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
Address
Stack
Sequence in which
registers are saved
(2) SP contains odd number
Address
Stack
Sequence in which
registers are saved
[SP] - 5 (Odd)
[SP] - 4 (Even)
[SP] - 3 (Odd)
[SP] - 2 (Even)
[SP] - 1 (Odd)
[SP] (Even)
PCL
PCM
FLGL
FLGH
PCH
[SP] - 5 (Even)
(2) All 16 bits saved
simultaneously
[SP] - 4 (Odd)
[SP] - 3 (Even)
(1) All 16 bits saved
simultaneously
[SP] - 2 (Odd)
[SP] - 1 (Even)
[SP]
Completed saving registers
in two operations.
(Odd)
Note :
1. [SP] denotes the initial value of the SP when an interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
PCL
PCM
FLGL
FLGH
PCH
(3)
(4)
Saved 8 bits at a time
(1)
(2)
Completed saving registers
in four operations.
PCL : 8 low-order bits of PC
PCM : 8 middle-order bits of PC
PCH : 4 high-order bits of PC
FLGL : 8 low-order bits of FLG
FLGH : 4 high-order bits of FLG
Figure 14.6 Register Save Operation
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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