M16C65 Datasheet, PDF (605/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
I2C0 control register 1 (S3D0)
b7
b0
ICK1 ICK0
SCL
M
SDA
M
PEC
PED
WIT
SIM
b7 ^{I2C0 address register 2(S0D2)} b0
SAD SAD SAD SAD SAD SAD SAD
6543210
b7 ^{I2C0 address register 1(S0D1)} b0
SAD SAD SAD SAD SAD SAD SAD
6543210
b7 ^{I2C0 status register 1(S11)} b0
AAS AAS AAS
210
b7 ^{I2C0 address register 0(S0D0)} b0
SAD SAD SAD SAD SAD SAD SAD
6543210
Interrupt
generator
SCL/SDA
interrupt
request
SA _{Address comparator}
D6
b7
b0
I2C0 data shift register (S00)
Interrupt
generator
I²C-bus
interface
interrupt
request
SDAMM
(SDA)
Noise filter
Data
controller
b7
b0
STSP
SEL
SIS
SIP
SSC SSC SSC SSC SSC
43210
I2C0 start/stop condition
control register (S2D0)
AL
circuit
BB
circuit
I2C0 status
register 0 (S10)
b7
b0
AL
AAS
ADR
0
LRB
MST TRX BB PIN
I2C0 control
register 2 (S4D0)
SCPI MSL
N AD
ICK4 ICK3 ICK2
TOS
EL
TOF
TOE
Timeout
detector
b7
TISS IHR
b0
ALS ES0 BC2 BC1 BC0
I2C0 control register 0
(S1D0)
SCLMM
(SCL)
Noise
filter
Clock
controller
b7
b0
ACK ACK FAST CCR CCR CCR CCR CCR
CLK BIT MODE 4 3 2 1 0
I2C0 clock control
register (S20)
Clock divider
I²C-bus system clock
(fVIIC)
System clock selector
PCLKR register
PCLK0=1
fIIC
f1IIC
f2IIC
PCLK0=0
Bit counter
Figure 25.1 Multi-master I²C-bus Interface Block Diagram
Table 25.3 I/O Ports
Pin Name
I/O Type
SDAMM
I/O
SCLMM
I/O
Function
I/O pin for SDA (N channel open drain output)
I/O pin for SCL (N channel open drain output)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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