M16C65 Datasheet, PDF (386/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
18. Timer B
18.3.3 Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Table 18.7 lists Specifications of Event Counter Mode, Table 18.8 lists Registers and the
Setting in Event Counter Mode, and Figure 18.5 shows Operation Example in Event Counter Mode.
Table 18.7 Specifications of Event Counter Mode
Item
Specification
Count source
• External signals input to TBiIN pin (active edge can be selected by a
program: rising edge, falling edge, or both rising and falling edges)
• Timer Bj overflow or underflow
Count operations
• Decrement
• When the timer underflows, it reloads the reload register contents and
continues counting.
Number of counts
--------1---------
(n + 1)
n: set value of the TBi register 0000h to FFFFh
Count start condition
Set the TBiS bit ⁽¹⁾ to 1 (start counting).
Count stop condition
Set the TBiS bit to 0 (stop counting).
Interrupt request
Timer underflow
generation timing
TBiIN pin function
Count source input
Read from timer
Count value can be read by reading the TBi register.
Write to timer
• When not counting
Value written to the TBi register is written to both reload register and counter.
• When counting
Value written to the TBi register is written to only reload register
(transferred to counter when reloaded next).
i = 0 to 5 j = i - 1, except j = 2 if i = 0, j = 5 if i = 3
Note:
1. Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are
assigned to bits 5 to 7 in the TBSR register.
Table 18.8 Registers and the Setting in Event Counter Mode ⁽¹⁾
Register
Bit
Setting
PCLKR
PCLK0
Set to 1.
CPSRF
CPSR
Write a 1 to reset the clock prescaler.
TBi1
7 to 0
- (setting unnecessary)
PPWFS1 to
PPWFS12 to
Set to 0.
PPWFS2
PPWFS10
PPWFS22 to
PPWFS20
TCKDIVC0
TCDIV00
Set to 0.
TBCS0 to TBCS3 7 to 0
Set to 00b.
TABSR
TBiS
Set to 1 when starting counting.
TBSR
Set to 0 when stopping counting.
TBi
7 to 0
Set the count value.
TBiMR
7 to 0
Refer to the TBiMR register below.
i = 0 to 5
Note:
1. This table does not describe a procedure.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 351 of 791