M16C65 Datasheet, PDF (459/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
20. Real-Time Clock
1s
BSY bit
TCSTF bit
in RTCCR1 register
1
RTCSEC
RTCMIN
RTCHR
RTCPM bit
IR bit in RTCCIC register
IR bit in RTCTIC register
44
Undefined
Compare value
match
45
23
Continue counting
Un-
defined
46
Continue using the count value
1
0
The bit becomes low when an interrupt request is accepted, or by
setting the bit to 0.
RTCOUT pin output
Output polarity inversion
The diagram above applies under the following conditions:
y The TOENA bit in the RTCCR1 register is 1 (compare output enabled).
y Bits RTCCMP1 to RTCCMP0 in the RTCCR2 register are 01b (compare 1 mode).
y Bits SEIE, MNIE, and HRIE in the RTCCR2 are 1 (compare by seconds, minutes, and hours. Interrupt enabled).
y Bits SCMP12 to SCMP10 and SCMP03 to SCMP00 in the RTCCSEC register are 4 and 5 respectively (second setting: 45).
Bits MCMP12 to MCMP10 and MCMP03 to MCMP00 in the RTCCMIN register are 2 and 3 respectively (minute setting: 23).
Bits HCMP11 to HCMP10 and HCMP03 to HCMP00 in the RTCCHR register are 0 and 1 respectively (hour setting: 1).
The PMCMP bit in the RTCCHR register is 0 (a.m.).
BSY bit : Bit in RTCSEC register
RTCSEC : Bits SC12 to SC10 and SC03 to SC00 in RTCSEC register
RTCMIN : Bits MN12 to MN10 and MN03 to MN00 in RTCMIN register
RTCHR : Bits HR11 to HR10 and HR03 to HR00 in RTCHR register
RTCPM bit : Bit in RTCCR1 register
Figure 20.8 Compare 1 Mode Operating Example
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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