M16C65 Datasheet, PDF (290/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
15. Watchdog Timer
15. Watchdog Timer
15.1 Introduction
The watchdog timer contains a 15-bit counter, and the count source protection mode (enabled/disabled)
can be set.
Table 15.1 shows Watchdog Timer Specification.
Refer to 6.4.8 “Watchdog Timer Reset” for details of watchdog timer reset.
Figure 15.1 shows Watchdog Timer Block Diagram.
Table 15.1 Watchdog Timer Specification
Item
Count Source Protection Mode Disabled Count Source Protection Mode Enabled
Count source
CPU clock
fOCO-S
Count operation
Decrement
Count start conditions Either of the following can be selected
(selected by the WDTON bit in the OFS1 address).
• Count automatically starts after reset.
• Count starts by writing to the WDTS register.
Count stop condition Stop mode, wait mode, bus hold
None
Watchdog timer
counter initial value
setting conditions
• Reset (Refer to 6. “Resets”)
• Write 00h, and then FFh to the WDTR register.
• Underflow
Operation when the Watchdog timer interrupt or watchdog Watchdog timer reset
timer underflows
timer reset
Selectable functions • Prescaler divide ratio
Divide-by-16 or divide-by-128 (selected by the WDC7 bit in the WDC register)
However, divide-by-2 is selected when the CM07 bit in the CM0 register is 1
(sub clock).
• Count source protection mode
Enabled or disabled (selected by the CSPROINI bit in the OFS1 address and
the CSPRO bit in the CSPR register)
Write to the WDTR register
Internal reset signal
(low active)
WDTR register written
WDTON bit
CPU clock
Bus hold
fOCO-S
Prescaler
1/16
WDC7
CM07
Refresh
1/128
1/2
CSPRO Watchdog timer counter
0
b14 b10
b3 b0
1
WDC4 to WDC0
Underflow
Figure 15.1 Watchdog Timer Block Diagram
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 255 of 791
PM12
0 _{Watchdog timer interrupt}
1 ^{Watchdog timer reset}