M16C65 Datasheet, PDF (368/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
17. Timer A
17.5.4 Timer A (Pulse Width Modulation Mode)
17.5.4.1 Register Setting
The timer is stopped after reset. Set the mode, count source, counter value, etc., using the TAiMR
register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR register,
registers TACS0 to TACS2, the TAPOFS register, TCKDIVC0 register, the PWMFS register, and the
PCLKR register before setting the TAiS bit in the TABSR register to 1 (count starts) (i = 0 to 4).
Always make sure the TAiMR register, bits TA0TGL and TA0TGH in the ONSF register, the TRGSR
register, registers TACS0 to TACS2, the TAPOFS register, TCKDIVC0 register, the PWMFS register,
and the PCLKR register are modified while the TAiS bit is 0 (count stops), regardless of whether after
reset or not.
17.5.4.2 Operating Mode Change
The IR bit is set to 1 when setting a timer operating mode with any of the following procedures:
• Selecting PWM mode or programmable output mode after reset
• Changing the operating mode from timer mode to PWM mode or programmable output mode
• Changing the operating mode from event counter mode to PWM mode or programmable output
mode
To use the timer Ai interrupt (IR bit), set the IR bit to 0 by a program after the changes listed above
are made.
17.5.4.3 Stop While Counting
When setting the TAiS bit to 0 (count stops) during PWM pulse output, the following actions occur.
When the POFSi bit in the TAPOFS register is 0:
• Counting stops.
• When the TAiOUT pin is high, the output level goes low and the IR bit is set to 1.
• When the TAiOUT pin is low, both the output level and the IR bit remain unchanged.
When the POFSi bit in the TAPOFS register is 1:
• Stop counting.
• If the TAiOUT pin output is low, the output level goes high and the IR bit is set to 1.
• If the TAiOUT pin output is high, both the output level and the IR bit remain unchanged.
17.5.4.4 Influence of SD
If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (three-
phase output forcible cutoff by input on the SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go
to the high-impedance state.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 333 of 791