M16C65 Datasheet, PDF (633/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
25.3.2 Generation of Start Condition
Follow the procedure below when the ES0 bit in the S1D0 register is 1 (I²C interface enabled) and the
BB bit in the S10 register is set to 0 (bus free). Figure 25.6 shows Start Condition Generation
Procedure.
(1) Write “E0h” to the S10 register.
The I²C interface enters the start condition standby state and the SDAMM pin is left open.
(2) Write a slave address to the S00 register.
A start condition is generated. Then, the bit counter becomes 000b, the SCL clock signal is output for
one byte, and the slave address is transmitted.
Write access to the S10 register is disabled during 1.5 fVIIC cycles after a stop condition is generated
and the BB bit becomes 0 (bus free). Therefore, when writing E0h to the S10 register and a slave
address to the S00 register during the 1.5 fVIIC cycles, start condition standby state is not entered, and
a start condition is not generated accordingly.
When generating a start condition immediately after the falling edge of the BB bit, check both TRX and
MST bits are 1 after the procedure (1), and then execute the procedure (2).
Start condition generated
Interrupt disabled
BB bit in the S10 register = 0?
1 (Bus busy)
Bus status checked
0 (Bus free)
Set E0h to the S10 register
Set slave address to the S00 register
Start condition standby
Start condition trigger generated
Interrupt enabled
Completed
Figure 25.6 Start Condition Generation Procedure
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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