M16C65 Datasheet, PDF (630/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25.3 Operations
25.3.1 Clock
Figure 25.5 shows I²C-bus Interface Clock.
25. Multi-Master I²C-bus Interface
PCLKR register
f1
Divide-by-2
f1IIC
f2IIC
PCLK0 = 1
fIIC
System clock select
circuit
Divide-by-m
I²C-bus system clock
fVIIC
PCLK0 = 0
S20 register
FASTMODE = 0
FASTMODE= 1
≠5
=5
CCR4 to CCR0
Divide-by-8
Divide-by-4
Divide-by-2
Divide-by-n
Clock control circuit
(1)
m: 2, 4, 8, 2.5, 3, 5, 6
(selectable by bits ICK1 to ICK0 in the S3D0 register and bits ICK4 to ICK2 in the S4D0 register)
n: 3 to 31 (setting values for bits CCR4 to CCR0 in the S20 register)
Note:
1. Select 100 kHz or below for the CPU clock in standard clock mode, and 400 kHz or below in high-speed clock mode.
Figure 25.5 I²C-bus Interface Clock
25.3.1.1 fVIIC
The fVIIC is determined by the setting combination of the following.
• The frequency of peripheral clock f1
• The PCLK0 bit in the PCLKR register
• Bits ICK1 to ICK0 in the S3D0 register
• Bits ICK4 to ICK2 in the S4D0 register
The fVIIC stops when the ES0 bit in the S1D0 register is 0 (I²C interface disabled).
Refer to Table 25.8 “I²C-bus System Clock Select Bits” for details.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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