M16C65 Datasheet, PDF (105/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
6. Resets
6.4.4 Voltage Monitor 0 Reset
This reset is triggered by the MCU's on-chip voltage detection 0 circuit. The voltage detection 0 circuit
monitors the voltage applied to the VCC1 pin (Vdet0).
The MCU resets the pins, CPU, and SFRs when the voltage applied to the VCC1 pin drops to Vdet0 or
below.
Then, the fOCO-S starts counting when the voltage applied to the VCC1 pin rises to Vdet0 or above.
The internal reset signal becomes high after 32 cycles of the fOCO-S, and then the MCU executes the
program at the address indicated by the reset vector. The fOCO-S divided by 8 is automatically
selected as the CPU clock after reset.
The CWR bit in the RSTFR register becomes 0 (cold start-up) after voltage monitor 0 reset. Refer to 4.
“Special Function Registers (SFRs)” for the remaining SFR states after reset.
The internal RAM is not reset. When the voltage applied to the VCC1 pin drops to Vdet0 or below while
writing data to the internal RAM, the internal RAM is in an undefined state.
Refer to 7. “Voltage Detector” for details of the voltage monitor 0 reset.
6.4.5 Voltage Monitor 1 Reset
This reset is triggered by the MCU's on-chip voltage detection 1 circuit. The voltage detection 1 circuit
monitors the voltage applied to the VCC1 pin (Vdet1).
When the VW1C6 bit in the VW1C register is 1 (voltage monitor 1 reset when Vdet1 passage is
detected), the MCU resets the pins, CPU, and SFRs when the voltage applied to the VCC1 pin drops to
Vdet1 or below. Then, after the set amount of time, the MCU executes the program at the address
indicated by the reset vector. The fOCO-S divided by 8 is automatically selected as the CPU clock after
reset.
The LVD1R bit in the RSTFR register becomes 1 (voltage monitor 1 reset detected) after voltage
monitor 1 reset. Some SFRs are not reset at voltage monitor 1 reset. Refer to 4. “Special Function
Registers (SFRs)” for details. The processor mode remains unchanged since bits PM01 to PM00 in the
PM0 register are not reset.
The internal RAM is not reset.
Refer to 7. “Voltage Detector” for details of the voltage monitor 1 reset.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 70 of 791