M16C65 Datasheet, PDF (366/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
17. Timer A
17.5.2 Timer A (Event Counter Mode)
17.5.2.1 Register Setting
The timer is stopped after reset. Set the mode, count source, counter value, etc., using the TAiMR
register, the TAi register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH in the ONSF register,
the TRGSR register, and the TAPOFS register before setting the TAiS bit in the TABSR register to 1
(count starts) (i = 0 to 4).
Always make sure the TAiMR register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH in the
ONSF register, the TRGSR register, and the TAPOFS register are modified while the TAiS bit is 0
(count stops), regardless of whether after reset or not.
17.5.2.2 Read from Timer
While counting is in progress, the counter value can be read at any time by reading the TAi register.
However, while reloading, FFFFh can be read in underflow, and 0000h in overflow. When the counter
is read before it starts counting and after a value is set in the TAi register while not counting, the set
value is read.
17.5.2.3 Influence of SD
If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is 1 (three-
phase output forcible cutoff by input on SD pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to
the high-impedance state.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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