M16C65 Datasheet, PDF (675/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
26. Consumer Electronics Control (CEC) Function
When the CABTWEN bit is set to 0:
Low pulse is immediately output regardless of the CEC signal state.
Receive error occurs
CEC
3 to 4 cycles of
count source
3.6 ms
When the CABTWEN bit is set to 1:
Low pulse is output at the riging edge of the CEC signal.
CEC
Receive error occurs
3.6 ms
Low pulse is output at the rising
edge within 3.6 ms after the receive
error occurs.
CEC
3 to 4 cycles of
count source
3.6 ms
If the low level lasts for 3.6 ms
or longer after the receive error
occurs, low pulse is not output
even if the rising edge is
detected thereafter.
The above diagram applies under the following condition.
y The CABTEN bit in the CECC4 register is set to 1 (low pulse output enabled in receive error).
CABTWEN: Bit in the CECC4 register
Figure 26.8 Low Pulse Output in Receive Error
26.3.5.3 ACK Bit Output
The output value of the 10th bit (ACK bit) can be selected.
When the CRACK bit in the CECC2 register is set to 0 (inserted by program), the value of the CCR-
BAO bit in the CCRB2 register is output as ACK data.
When the CRACK bit is set to 1 (inserted by hardware), ACK is output when the received Destination
address matches the address selected by the CRADRI1 or CRADRI2 register (own address). Table
26.8 lists ACK Output.
Table 26.8 ACK Output
CRACK CCRBAO
Bit
Bit
0
0
1
1
-
Received Destination
Address
-
-
Directly address
(0000b to1110b)
Broadcast address
(1111b)
Destination Address
Address selected by the CRADRI1 or
CRADRI2 Register (Own Address)
ACK
Output
-
ACK
-
NACK
Matches received Destination address
ACK
Not match received Destination address
NACK
1111b (matches received Destination address) ACK
0000b to 1110b
NACK
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 640 of 791