M16C65 Datasheet, PDF (555/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
(1) 8-bit Data Transmit Timing (with a Parity and 1 Stop Bit)
The transmit/receive clock stops once because a high-level signal is applied to the CTS
pin when the stop bit is verified. The transmit/receive clock resumes running as soon as a
Tc
low-level signal is applied to the CTS pin.
Transmit/receive
clock
TE bit in ¹
UiC1 register 0
TI bit in ¹
UiC1 register ₀
High
CTSi
Low
TXDi
TXEPT bit in ¹
UiC0 register ₀
IR bit in ¹
SiTIC register ₀
Set the data in the UiTB register.
Data is transferred from the UiTB register
to the UARTi transmit register.
Start bit
Parity Stop
bit
bit
Pulse stops because the TE
bit is set to 0.
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1
Set to 0 by an interrupt request acknowledgement or by a program.
i = 0 to 2, 5 to 7
The above timing diagram applies when the register bits are set as follows:
· The PRYE bit in the UiMR register = 1 (parity enabled)
· The STPS bit in the UiMR register = 0 (1 stop bit)
· The CRD bit in the UiC0 register = 0 (CTS/RTS enabled)
· The CRS bit in the UiC0 register
= 0 (CTS selected)
· The UiIRS bit in the UiC1 register = 1 (an interrupt request occurs when transmit completed)
Tc = 16(n + 1)/fj or 16(n + 1)/fEXT
fj : Frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : Frequency of UiBRG count source (external clock)
n : Value set to UiBRG
(2) 9-bit Data Transmit Timing (with No Parity and 2 Stop Bits)
Tc
Transmit/receive
clock
TE bit in ¹
UiC1 register ₀
TI bit in ¹
UiC1 register
0
TXDi
Set the data in the UiTB register.
Start bit
Data is transferred from the UiTB register
to the UARTi transmit register.
Stop Stop
bit
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1
TXEPT bit in ¹
UiC0 register ₀
IR bit in ¹
SiTIC register ₀
Set to 0 by an interrupt request acknowledgement or by a program.
i = 0 to 2, 5 to 7
The above timing diagram applies when the register bits are set as follows:
· The PRYE bit in the UiMR register = 0 (parity disabled)
· The STPS bit in the UiMR register = 1 (2 stop bits)
· The CRD bit in the UiC0 register = 1 (CTS/RTS disabled)
· The UiIRS bit in the UiC1 register = 0 (an interrupt request occurs when transmit
buffer becomes empty)
TC = 16(n + 1)/fj or 16(n + 1)/fEXT
fj : Frequency of UiBRG count source
(f1SIO, f2SIO, f8SIO, f32SIO)
fEXT: Frequency of UiBRG count source (external clock)
n : Value set to UiBRG
Figure 23.12 Transmit Timing in UART Mode
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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