M16C65 Datasheet, PDF (514/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
22. Remote Control Signal Receiver
PMCi internal input signal
EN bit
Counter operation
Count starts
Counter value
a
b
c
d
e
Bits TYP1 to TYP0 are 00b (period measurement (between rising edge and rising edge)
PMCiTIM register
b
d
FFFFh
f
f
IR bit
CEFLG bit
The bit becomes 0 when an
interrupt request is accepted, or
by setting the bit to 0.
Bits TYP1 to TYP0 are 01b (period measurement between falling edge and falling edge)
PMCiTIM register
a
c
e
IR bit
CEFLG bit
Bits TYP1 to TYP0 are 10b (pulse width measurement)
PMCiTIM register
a
b
c
d
The bit becomes 0 when an
interrupt request is accepted, or
by setting the bit to 0.
e
f
IR bit
The bit becomes 0 when an
interrupt request is accepted, or
by setting the bit to 0.
CEFLG bit
i = 0, 1
The above diagram shows an instance in which the following condition is met:
y The TIMINT bit in the PMCiINT register is 1 (timer measure interrupt enabled)
Figure 22.9 Difference of Operations in Receive Modes (Input Capture Mode)
22.3.4.1 Count Operation
In input capture mode, the counter counts from 0000h to FFFFh, and then return to 0000h to continue
counting.
When the counter becomes 0000h after FFFFh, the CEFLG bit in the PMCiCON2 register becomes 1
(counter overflow) and holds 1 until the next measurement timing.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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