M16C65 Datasheet, PDF (211/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
11. Bus
(1) Separate Bus, No Wait States
Bus cycle = 2φ
Bus cycle = 2φ
BCLK
Address
CSi
Data
RD
WR, WRL, WRH
A
WD
A
RD
(Note 1)
(2) Separate Bus, One Wait State (1φ + 1φ)
Bus cycle = 2φ
BCLK
Address
CSi
Data
RD
WR, WRL, WRH
A
WD
Bus cycle = 2φ
A
RD
(Note 1)
(3) Separate Bus, Two Wait States (1φ + 2φ)
Bus cycle = 3φ
BCLK
Address
A
CSi
Data
WD
RD
WR, WRL, WRH
Bus cycle = 3φ
A
RD
(Note 1)
Figure 11.6
i = 0 to 3
A : Address RD : Read data (input) WD : Write data (output)
Note:
1. When accessing consecutively to the same chip-select area, CSi keeps ouputting low level.
Typical Bus Timings Using Software Wait States (1/4)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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