M16C65 Datasheet, PDF (275/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
14. Interrupts
14.7.2 Interrupt Sequence
The interrupt sequence is explained here. The sequence starts when an interrupt request is accepted
and ends when the interrupt routine is executed.
If an interrupt request occurs during execution of an instruction, the processor determines its priority
after the execution of the instruction is completed, and transfers control to the interrupt sequence from
the next cycle. However, if an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR,
or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers
control to the interrupt sequence.
The CPU behavior during the interrupt sequence is described below. Figure 14.3 shows Time Required
for Executing Interrupt Sequence.
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading
address 00000h. Then, the IR bit applicable to the interrupt information is set to 0 (interrupt not
requested).
(2) The FLG register, prior to the interrupt sequence, is saved to a temporary register ⁽¹⁾ within the
CPU.
(3) Flags I, D, and U in the FLG register are set as follows:
• The I flag is set to 0 (interrupt disabled)
• The D flag is set to 0 (single-step interrupt disabled).
• The U flag is set to 0 (ISP selected).
Note that the U flag does not change states when an INT instruction for software interrupt numbers
32 to 63 is executed.
(4) The temporary register ⁽¹⁾ within the CPU is saved on the stack.
(5) The PC is saved on the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, an instruction is executed from the starting address of the
interrupt routine.
Note:
1. Temporary registers cannot be modified by users.
1
2
3
4
CPU clock
Address bus
Data bus
RD
WR ⁽²⁾
Address 00000h
Interrupt
information
5
6
7
8
Undefined ⁽¹⁾
Undefined ⁽¹⁾
Undefined ⁽¹⁾
9
10 11
12 13
14
15
16
17 18
SP-2
SP-4
vec
vec+2
PC
SP-2
contents
SP-4
contents
vec
contents
vec+2
contents
Notes :
1. The undefined state depends on the instruction queue buffer. A read cycle is generated when
the instruction queue buffer is ready to accept instructions.
2. The WR signal timing shown here applies when the stack is located in the internal RAM.
Figure 14.3 Time Required for Executing Interrupt Sequence
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 240 of 791