M16C65 Datasheet, PDF (614/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
CCR4-CCR0 (Bit Rate Control Bit) (b4-b0)
The setting range of bits CCR4 to CCR0 (CCR value) is 0 to 31. If the setting values of bits CCR4 to
CCR0 are the CCR value (CCR value: 3 to 31), the bit rate can be determined by the following
equations.
Refer to 25.3.1.2 “Bit Rate and Duty Cycle” for more details.
In standard speed clock mode,
Bit rate= ₈-----_×-----_C----^f-_C-^V---_R-^I--^I--^C--_v----_a---_l--_u----_e- ≤ 100 kbps
When the CCR value is other than 5 in high-speed clock mode,
Bit rate= ₄-----_×-----_C----^f-_C-^V---_R-^I--^I--^C--_v----_a---_l--_u----_e- ≤ 400 kbps
When the CCR value is 5 in high-speed clock mode, the bit rate is assumed to reach 400 kbps, the
maximum bit rate in high-speed clock mode.
Bit
rate=
--------------^f--^V----^I--^I--^C----------------
2 × CCR value
=
f---V----I--I--C---
10
≤ 400
kbps
The CCR value should not be set to 0 to 2 regardless of the fVIIC frequency.
Bits CCR4 to CCR0 should not be rewritten during transmission/reception.
FASTMODE (SCL Mode Select Bit) (b5)
When using the high-speed clock mode I²C-bus standard (400 kbps at maximum), set the FASTMODE
bit to 1 (high-speed clock mode) and set fVIIC at 4 MHz or more.
The FASTMODE bit should not be rewritten during transmission/reception.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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