M16C65 Datasheet, PDF (631/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
25.3.1.2 Bit Rate and Duty Cycle
Bit rate is determined by the setting combination of the fVIIC and bits CCR4 to CCR0 in the S20
register.
Table 25.11 lists Bit Rate of Internal SCL Output and Duty Cycle. Even if there is a change in duty
cycle, the bit rate does not change. The bit rate and duty cycle described here are the ones before
the I²C interface have any effect from the SCL output of external device.
Table 25.11 Bit Rate of Internal SCL Output and Duty Cycle
Item
Standard Clock Mode
High-Speed Clock Mode
(CCR value = other than 5)
Bit rate (bps)
8^-----×^-----C^---f--CV^{----IR--I--C---}v^---a^---l^--u^---e^--
4^-----×^-----C^---f--CV^{----IR--I--C---}v^---a^---l^--u^---e^--
High-Speed Clock Mode
(CCR value = 5)
------------^f--^V-----^I--^I--^C-------------- = ^{f---V----I--I--C---}
2 × CCRvalue 10
Duty cycle
50% ⁽¹⁾
50% ⁽²⁾
CCR value: Setting value of bits CCR4 to CCR0
Notes:
1. Fluctuation of high level: -4 to +2 fVIIC cycles
2. Fluctuation of high level: -2 to +2 fVIIC cycles
35 to 45%
When the setting value (CCR value) of bits CCR4 to CCR0 is 5 (00100b) in high-speed clock mode, the
maximum bit rate should be 400 kbps in high-speed clock mode.
The bit rate and duty cycle are as follows.
• Bit rate:
-------------^f--^V----^I--^I--^C---------------- = -^f--^V----^I--^I--^C---
2 × CCR value 10
When fVIIC is 4 MHz, the bit rate is 400 kbps.
• Duty cycle is 35 to 45%
Even if the bit rate is 400 kbps, the minimum low period of SCLMM clock of 1.3 μs (I²C-bus standard) is
ensured.
Table 25.12 lists Bit Setting of Bits CCR4 to CCR0 and Bit Rate (fVIIC = 4 MHz).
Table 25.12 Bit Setting of Bits CCR4 to CCR0 and Bit Rate (fVIIC = 4 MHz)
Bits CCR4 to CCR0 in the S20 Register
Bit Rate (kbps)
CCR4 CCR3 CCR2 CCR1 CCR0
Standard Clock Mode
High-Speed Clock Mode
0
0
0
0
0
Do not set ⁽¹⁾
Do not set ⁽¹⁾
0
0
0
0
1
Do not set ⁽¹⁾
Do not set ⁽¹⁾
0
0
0
1
0
Do not set ⁽¹⁾
Do not set ⁽¹⁾
0
0
0
1
1
Do not set ⁽²⁾
333
0
0
1
0
0
Do not set ⁽²⁾
250
0
0
1
0
1
100
400
0
0
1
1
0
83.3
166
:
:
:
:
:
:
:
1
1
1
0
1
17.2
34.5
1
1
1
1
0
16.6
33.3
1
1
1
1
1
16.1
32.3
Notes:
1.
2.
Bits CCR4 to CCR0 should not be set to 0 to 2 regardless of the fVIIC frequency.
The maximum bit rate is 100 kbps in standard clock mode and 400 kbps in high-speed clock
mode. Do not exceed the maximum bit rate.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 596 of 791