M16C65 Datasheet, PDF (518/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
22. Remote Control Signal Receiver
22.4 Interrupt
The remote control signal receiver has remote control signal receiver 0 interrupt and remote control signal
receiver 1 interrupt. The remote control signal receiver 0 interrupt and remote control signal receiver 1
interrupt are interrupts in PMC0 and PMC1 respectively.
A remote control signal receiver i interrupt request signal is generated every time the conditions are met.
If the interrupt enable bit in the PMCiCON2 or PMCiINT register is 1, the IR bit in the PMCiIC register
becomes 1 (interrupt request) when the corresponding interrupt request signal is generated. Table 22.21
lists Interrupt Source of Remote Control Signal Receiver i Interrupt (i = 0, 1).
Table 22.21 Interrupt Source of Remote Control Signal Receiver i Interrupt (i = 0, 1)
Mode Interrupt Source
Interrupt Request Generating Condition
Interrupt enable bit
Register
Bit
Pattern Completion of data Counter value is larger than values of
PMCiINT DRINT
match reception
registers PMCiHDPMAX, PMCiD0PMAX, and
mode
PMCiD1PMAX
Header match
The measured result is within the range set by PMCiINT PTHDINT
registers PMCiHDPMIN and PMCiHDPMAX
(when header is enabled)
Data 0/1 match
The measured result is within the range set by PMCiINT PTDINT
registers PMCiD0PMIN and PMCiD0PMAX or
registers PMCiD1PMIN and PMCiD1PMAX
Special data match The measured result is within the range set by PMC0INT SDINT
registers PMCiHDPMIN and PMCiHDPMAX
(when special data is enabled)
Receive error
Input signal width is none of header, data 0, PMCiINT REINT
data 1, and special data
Data 0 or data 1 is detected before detecting
header when the HDEN bit is 1
Receive buffer full The value of the PMC0RBIT register is 48 PMC0INT BFULINT
Compare match The values of registers PMC0CPD and
PMC0INT CPINT
PMC0DAT0 are matched (only bits selected
by the CPN bit in the PMC0CPC register are
compared)
Timer measurement Measurement end edge of PMCi internal input PMCiINT TIMINT
signal
Input Timer measurement Measurement end edge of PMCi internal input PMCiINT TIMINT
capture
signal
mode
Counter overflow
Counter overflow (counter value exceeds
FFFFh and becomes 0000h)
PMCiCON2 CEINT
Measured result: Content of the PMCiTIM register
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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