M16C65 Datasheet, PDF (481/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
22. Remote Control Signal Receiver
EHOLD (Error Flag Hold Bit) (b3)
When receive error occurs, period when the REFLG bit in the PMC0STS register holds 1 (receive error)
can be selected. Refer to “REFLG (Receive Error Flag) (b1)” in 22.2.5 “PMCi Status Register
(PMCiSTS) (i = 0, 1)” for details.
HDEN (Header Pattern Enable Bit) (b4)
If the HDEN bit is set to 1 (header enabled), the following occur when detecting data 0, data 1, or
special data before detecting header.
• The REFLG bit in the PMCiSTS register becomes 1 (error occurs)
• Bits PTD0FLG, PTD1FLG, and SDFLG in the PMCiSTS register remain unchanged.
• Registers PMCDAT0 to PMCDAT5 remain unchanged.
DRINT1-DRINT0 (Receive Interrupt Control Bit) (b7-b6)
A condition for generating a data reception complete interrupt request can be selected.
Set the DRINT bit in the PMC0INT register to 1 (reception complete interrupt enabled) after setting bits
DRINT1 to DRINT0.
When setting the DRINT1 bit to 1, set the EHOLD bit in the PMC0CON0 register to 1 (hold the REFLG
bit state after next data received).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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