M16C65 Datasheet, PDF (417/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
19. Three-Phase Motor Control Timer Function
19.3.1.8 Three-Phase Output Forced Cutoff Function
While the INV02 bit in the INVC0 register is 1 (three-phase motor control timer function) and the
INV03 bit is 1 (three-phase motor control timer output enabled), when a low-level signal is applied to
the SD pin, the INV03 bit in the INVC0 register becomes 0 (three-phase motor control timer output
disabled), and pins corresponding to U, U, V, V, W and W outputs change all together as follows:
• When the IVPCR1 bit in the TB2SC register is 1 (three-phase output forced cutoff enabled)
High-impedance state
• When the IVPCR1 bit in the TB2SC register is 0 (three-phase output forced cutoff disabled)
I/O ports or other peripheral function I/O ports
However, applying a low-level signal to the SD pin while the IVPCR1 bit is 1 places the pins in a high-
impedance state even when the pins are used as functions other than U, U, V, V, W and W outputs.
Table 19.7 lists State of Pins U, U, V, V, W, and W.
Table 19.7 State of Pins U, U, V, V, W, and W
State of Bit and Pin
IVPCR1 bit in TB2SC
register
SD input
Function or State of Pins U, U, V, V, W and W
High
Three-phase PWM output
1
Low
High-impedance
High
Three-phase PWM output
0
Low
I/O port or other peripheral functions
Note:
1. In the above case, bits INVC02, INVC03 and PFCi are all 1.
The digital filter is available for the SD pin. When the value of bits NMIDF2 to NMIDF0 in the NMIDF
register is other than 000b (digital filter enabled), the SD level is sampled for every sampling clock.
When the same sampled level is detected three times in a row, the level is transferred to the internal
circuit. Refer to 13.4.3 “NMI/SD Digital Filter”.
To return the pin function to the three-phase PWM output after the forced cutoff, follow these steps
below:
(1) Apply a high-level signal to the SD pin.
(2) Wait for more than three cycles of the digital filter sampling clock.
(3) Set the INV03 bit in the INVC0 register to 1 (three-phase motor control timer output enabled).
(4) Confirm that the INV03 bit is 1. If the bit is 0, return to step 3.
(5) Set the IVPCR1 bit to 0 (three-phase output forced cutoff disabled).
(6) Set the IVPCR1 bit to 1 (when enabling three-phase output forced cutoff again).
When not using the three-phase output forced cutoff function, set a port direction bit which shares the
pin with SD input to 0 (input port), and apply a high-level signal to the SD pin.
The same pin is used for both SD input and NMI input. To disable the NMI interrupt, set the PM24 bit
in the PM2 register to 0 (NMI interrupt disabled).
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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