M16C65 Datasheet, PDF (59/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
1. Overview
1.6 Pin Functions
Table 1.15 Pin Functions (128-Pin Package) (1/3)
Signal Name
Power supply
input
Pin Name
VCC1
VCC2
VSS
I/O Power Supply
Description
I-
Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 ≥ VCC2)
and 0 V to the VSS pin. ⁽¹⁾
Analog power
supply input
Reset input
CNVSS
AVCC
AVSS
RESET
CNVSS
External data
bus width
select input
BYTE
I VCC1
I VCC1
I VCC1
I VCC1
Apply the power supply for the A/D converter. Connect the
AVCC pin to VCC1. Connect the AVSS pin to VSS.
Low active input pin. Driving this pin low resets the MCU.
Input pin to switch processor mode. Connect the CNVSS pin to
VSS via a resistor to start up after a reset in single-chip mode.
To start up in microprocessor mode, connect it to VCC1.
Input pin to select the data bus of the external area. The data
bus is 16 bits when it is low and 8 bits when it is high. This
pin must be fixed either high or low. Connect the BYTE pin to
VSS in single-chip mode.
Bus control
pins
D0 to D7
I/O VCC2
Inputs or outputs data (D0 to D7) while accessing an
external area with separate bus
D8 to D15
I/O VCC2
Inputs or outputs data (D8 to D15) while accessing an
external area with 16-bit separate bus
A0 to A19
O VCC2
Outputs address bits A0 to A19
A0/D0 to
A7/D7
I/O VCC2
A1/D0 to
A8/D7
I/O VCC2
CS0 to CS3 O VCC2
WRL/WR
WRH/BHE
RD
O VCC2
Inputs or outputs data (D0 to D7) and outputs address bits
(A0 to A7) by timesharing, while accessing an external area
with 8-bit multiplexed bus
Inputs or outputs data (D0 to D7) and outputs address bits
(A1 to A8) by timesharing, while accessing an external area
with 16-bit multiplexed bus
Outputs chip-select signals CS0 to CS3 to specify an
external area
Low active output pins. Outputs WRL, WRH, (WR, BHE), RD
signals. WRL and WRH can be switched with BHE and WR
by a program.
• WRL, WRH and RD selected
If the external data bus is 16 bits, data is written to an even
address in external area when WRL is driven low. Data is
written to an odd address when WRH is driven low. Data is
read when RD is driven low.
• WR, BHE and RD selected
Data is written to external area when WR is driven low.
Data in external area is read when RD is driven low. An
odd address is accessed when BHE is driven low. Select
WR, BHE, and RD for external 8-bit data bus.
ALE
O VCC2
Output ALE signal to latch address.
HOLD
I VCC2
Low active input pin. The MCU is placed in hold state while
the HOLD pin is driven low.
HLDA
O VCC2
Low active output pin. In a hold state, HLDA outputs a low-
level signal.
RDY
I VCC2
Low active input pin. The MCU bus is placed in wait state
while the RDY pin is driven low.
Power supply: VCC2 is used to supply power to external bus associated pins. The dual power supply configuration
allows VCC2 to interface at a different voltage than VCC1.
Note:
1. VCC1 is hereinafter referred to as VCC unless otherwise noted.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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