M16C65 Datasheet, PDF (210/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
11. Bus
11.3.5.10 Software Wait States
The PM17 bit in the PM1 register, which is a software-wait-related bit, affects both the internal
memory and the external area.
Software wait states can be inserted to the external area by setting the PM17 bit or setting the CSiW
bit in the CSR register or bits CSEi1W to CSEi0W in the CSE register for each CSi (i = 0 to 3). To use
the RDY signal, set the corresponding CSiW bit to 0 (wait state). Refer to Table 11.11 “Bits and Bus
Cycles Related to Software Wait States (External Area)”, for details.
Table 11.11 Bits and Bus Cycles Related to Software Wait States (External Area)
Area
Bus Mode
Setting of Software-Wait-Related Bits Software Bus Cycles
PM17 CSiW
CSEi1W, EWCi1, ^Wait
CSEi0W EWCi0 Cycles
External Separate 0
1
00b
-
None
1 BCLK cycle
area
bus
(read)
2 BCLK cycles
(write)
-
0
00b
-
1 (1φ + 1φ) _{2 BCLK cycles} ⁽⁴⁾
-
0
01b
-
2 (1φ + 2φ) 3 BCLK cycles
-
0
10b
-
3 (1φ + 3φ) 4 BCLK cycles
-
0
11b
00b
(2φ + 3φ) 5 BCLK cycles
01b
(2φ + 4φ) 6 BCLK cycles
10b
(3φ + 4φ) 7 BCLK cycles
11b
(4φ + 5φ) 9 BCLK cycles
1
0 ⁽³⁾
00b
-
1 (1φ + 1φ) 2 BCLK cycles
Multiplexed -
0 ⁽²⁾
00b
-
1
bus
-
0 ⁽²⁾
01b
-
2
3 BCLK cycles
3 BCLK cycles
-
0 ⁽²⁾
10b
-
3
4 BCLK cycles
1
0 ^{(2), (3) 00b}
-
1
3 BCLK cycles
i = 0 to 3
− indicates that either 0 or 1 can be set.
PM17: Bit in the PM1 register
CSiW: Bits in the CSR register ⁽¹⁾
CSEi1W, CSEi0W: Bits in the CSE register
EWCi1, EWCi0: Bits in the EWC register
Notes:
1. To use the RDY signal, set the CSiW bit to 0 (wait state).
2. To access in multiplexed bus mode, set the CSiW bit to 0 (wait state).
3. To access an external area when the PM17 bit is 1, set the CSiW bit to 0 (wait state).
4. After reset, the PM17 bit is set to 0 (no wait state), bits CS0W to CS3W are set to 0 (wait state),
and the CSE register is set to 00h (one wait state for CS0 to CS3). Therefore, all external areas
are accessed with one wait state.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 175 of 791