M16C65 Datasheet, PDF (337/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
17. Timer A
17.3.1.3 Count Source
Internal clocks are counted in timer mode, one-shot timer mode, PWM mode, and programmable
output mode. (Refer to Figure 17.1 “Timer A and B Count Sources”.) Table 17.5 lists Timer A Count
Source.
Timer A, B, and multi-master I²C-bus interface share the divider. f1 or fOCO-F can be selected before
the timer AB divider.
f1 is any of the following. Select f1 by the CM21 bit in the CM2 register and the FRA01 bit in the FRA0
register. (Refer to 8. “Clock Generator”.)
• Main clock divided by 1 (no division)
• PLL clock divided by 1 (no division)
• fOCO-S divided by 1 (no division)
• fOCO-F divided by 1 (no division)
Table 17.5 Timer A Count Source
Bit Set Value
Count Source
TCS3
PCLK0
TCS7
TCS2 to
TCS0
TCS4 to
TCS6
TCK1 to TCK0
Remarks
f1TIMAB
1
0
-
00b
f1 or fOCO-F ⁽¹⁾
1
000b
-
f2TIMAB
0
0
-
00b
f1 divided by 2 or
1
000b
-
fOCO-F divided by 2 ⁽¹⁾
f8TIMAB
-
0
-
01b
f1 divided by 8 or
1
001b
-
fOCO-F divided by 8 ⁽¹⁾
f32TIMAB
-
0
-
10b
f1 divided by 32 or
1
010b
-
fOCO-F divided by 32 ⁽¹⁾
f64TIMAB
-
1
011b
-
f1 divided by 64 or
fOCO-F divided by 64 ⁽¹⁾
fOCO-F
-
1
100b
-
fOCO-F
fOCO-S
-
1
101b
-
fOCO-S
fC32
-
0
-
11b
fC32
1
110b
-
PCLK0: Bit in the PCLKR register
TCS7 to TCS0: Bits in registers TACS0 to TACS2
TCK1 to TCK0: Bits in the TAiMR register (i = 0 to 4)
Note:
1. Select f1 or fOCO-F by the TCDIV00 bit in the TCKDIVC0 register.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 302 of 791