M16C65 Datasheet, PDF (608/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25.2.2 I2C0 Data Shift Register (S00)
25. Multi-Master I²C-bus Interface
I2C0 Data Shift Register
b7
b0
Symbol
S00
Address
02B0h
Function
Transmit/receive data is stored.
After Reset
Undefined
RW
RW
When the I²C interface is a transmitter, write a transmit data to the S00 register. When the I²C interface
is a receiver, a received data can be read from the S00 register. In master mode, this register is used to
generate a start condition or stop condition on a bus. (Refer to 25.3.2 “Generation of Start Condition”
and 25.3.3 “Generation of Stop Condition”.)
Write to the S00 register when the ES0 bit in the S1D0 register is set to 1 (I²C interface enabled).
The S00 register should not be written when data transmission/reception is in progress.
When the I²C interface is a transmitter, the data written in the S00 register is transmitted to other
devices. The MSB (bit 7) is transmitted first, synchronizing with the SCLMM clock. Every time one-bit
data is output, the content of the S00 register is one-bit shifted to the left.
When the I²C interface is a receiver, a data is transferred to the S00 register from other devices. The
LSB (bit 0) is input first, synchronizing with the SCLMM clock. Every time one-bit data is output, the
content of the S00 register is one-bit shifted to the left. Figure 25.2 shows Timing to Store The Received
Data into The S00 Register.
SCLMM
SDAMM
tdfil
Internal SCL
Internal SDA
Shift clock
(Internal signal)
S00 register
tdfil
tdsft
Data
Data is stored into the bit 0 at the rising edge of shift clock
Data
tdfil: Noise filter delay time, 1 to 2 fVIIC cycles
tdsft: Shift clock delay time, 1 fVIIC cycle
Data shifts for one bit to the left
Figure 25.2 Timing to Store The Received Data into The S00 Register
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 573 of 791