M16C65 Datasheet, PDF (789/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
31.9 Notes on Bus
Note
Do not use bus control pins for the 80-pin package.
31. Precautions
31.9.1 Reading Data Flash
When 2.7 V ≤ VCC1 ≤ 3.0 V and f(BCLK) ≥ 16 MHz, or when 3.0 V < VCC1 ≤ 5.5 V and f(BCLK) ≥ 20
MHz, one wait state is necessary to read data flash. Use the PM17 bit or the FMR17 bit to specify one
wait state.
31.9.2 External Bus
When a hardware reset, power-on reset or voltage monitor 0 reset is performed with a high-level input
on the CNVSS pin, contents of internal ROM cannot be read.
31.9.3 External Access Soon After Writing to the SFRs
When writing to the SFRs is followed by accessing to an external device, the write signal and CSi signal
switch simultaneously. Thus, adjust the capacity of individual signal not to make a write signal delay.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 754 of 791