M16C65 Datasheet, PDF (603/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
25. Multi-Master I²C-bus Interface
25. Multi-Master I²C-bus Interface
25.1 Introduction
The multi-master I²C-bus interface (I²C interface) is a serial communication circuit based on I²C-bus data
transmit/receive format, equipped with arbitration lost detection and clock synchronous functions.
Table 25.1 lists Multi-master I²C-bus Interface Specification, Table 25.2 lists Detections of I²C Interface,
Figure 25.1 shows Multi-master I²C-bus Interface Block Diagram, and Table 25.3 lists I/O Ports.
Table 25.1 Multi-master I²C-bus Interface Specification
Item
Function
Format
Based on I²C-bus standard:
7-bit addressing format
High-speed clock mode
Standard clock mode
Communication mode
Based on I²C-bus standard:
Master-transmitter
Master-receiver
Slave-transmitter
Slave-receiver
Bit rate
16.1 kbps to 400 kbps (fVIIC = 4 MHz)
I/O pin
Serial data line SDAMM (SDA)
Serial clock line SCLMM (SCL)
Interrupt request generating _I²_{C-bus interrupt}
source
Completion of transmission
Completion of reception
Slave address match detection
General call detection
Stop condition detection
Timeout detection
• SDA/SCL interrupt
Rising or falling edge of the SDAMM/SCLMM line
Selectable functions
• I²C-bus interface pin input level select
Selectable input level with I²C-bus input level or SMBus input level
• SDA/port, SCL/port selection
A function to change pins SDAMM and SCLMM to output ports
respectively.
• Timeout detection
A function to detect that SCLMM pin is driven high for over a certain period
of time when the bus is busy.
• Free format select
A function to generate an interrupt request when receiving the 1st byte
data, regardless of the slave address value.
fVIIC: I²C-bus system clock
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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