M16C65 Datasheet, PDF (134/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
8. Clock Generator
CM10 = 1
(stop mode)
SQ
R
Sub-clock
oscillation circuit
XCIN
XCOUT
CM04
FRA00
CM14
40 MHz
on-chip
oscillator
125 kHz
on-chip
oscillator
XIN XOUT
CM05
Main
clock
Main clock
oscillation circuit
Subclock
I/O ports
CM01 to CM00 = 00b, PCLK5 = 0
PM01 to PM00 = 00b, CM01 to CM00 = 01b, PCLK5 = 0
PM01 to PM00 = 00b,
CM01 to CM00 = 10b, PCLK5 = 0
f8
CLKOUT
PM01 to PM00 = 00b,
PM01 to PM00 = 00b, _{CM01 to CM00 = 00b,}
CM01 to CM00 = 11b, PCLK5 = 0 _{PCLK5 = 1}
f32
fC
1/32
fOCO40M
fC
1/2
fOCO-S
Oscillation
stop/re-
oscillation
detection
circuit
PLL frequency
synthesizer
PLL clock
1 ^CM11
fOCO-F
1 FRA01
0
1 ^CM21
0
bc
1 ^CM07
a
d
Divider
0
fC32
fOCO40M
Peripheral
function
clock
fOCO-F
fOCO-S
f1
CPU clock
BCLK
0
CM02
SQ
WAIT
R
instruction
b
c
RESET
Software reset
NMI
PM24
Interrupt request level judgement output
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
Voltage monitor 1 interrupt
Voltage monitor 2 interrupt
Watchdog timer reset
Oscillation stop detect reset
CM00 to CM04, CM05 to CM07
: Bits in the CM0 register
CM10, CM11, CM14, CM16, CM17 : Bits in the CM1 register
PCLK5
: Bit in the PCLKR register
CM21, CM27
: Bits in the CM2 register
PM00, PM01
: Bits in the PM0 register
PM24
: Bit in the PM2 register
FRA00, FRA01 : Bits in the FRA0 register
a
1/2
1/2
1/2
1/2
1/2
1/32
1/2
CM06 = 0
CM17 to
CM16 = 01b
1/4
CM06 = 0
CM17 to CM16
= 10b
1/8
CM06 = 1
1/16
CM06 = 0
CM17 to CM16 = 11b
d
CM06 = 0, CM17 to CM16 = 00b
Detail of Divider
Oscillation Stop/Re-Oscillation Detection Circuit
Main
Clock
Pulse generation
circuit for clock
edge detection
and charge/
discharge control
Charge/
discharge
circuit
CM27 = 0
CM27 = 1
Reset
generation
circuit
Oscillation stop/
re-oscillation
detection interrupt
generation circuit
Oscillation stop
detection reset
Oscillation stop/
re-oscillation
detection interrupt
signal
CM21 switch signal
PLL Frequency Synthesizer
Main
Clock
1/32
Reference
clock divider
Phase
comparator
Charge
pump
Figure 8.1 System Clock Generator Circuitry
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
Page 99 of 791
Voltage
control
oscillator
(VCO)
Divider
PLL clock
Internal
lowpass filter