M16C65 Datasheet, PDF (488/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
22. Remote Control Signal Receiver
CPFLG (Compare Match Flag) (b0)
This bit is valid when the CPEN bit in the PMC0CPC register is set to 1 (compare enabled).
Condition to become 0:
• When the DRFLG bit in the PMC0STS register changes from 0 to 1 (next frame reception starts).
• When the 48th bit is received after the CPFLG bit becomes 1, and then (the DRFLG bit remains 1
(receiving)) no compare match occurs after receiving bit n (n = value set by bits CPN2 to CPN0 in
the PMC0CPC register)
Condition to become 1:
• The PMC0CPD register matches the PMC0DAT0 register (when the setting value of bits CPN2 to
CPN0 in the PMC0CPC register is n, bits n to 0 in the PMC0CPD register matches bits n to 0 in the
PMC0DAT0 register).
REFLG (Receive Error Flag) (b1)
The REFLG bit is a flag indicating receive error. Conditions for changing the REFLG bit are affected by
the HDEN bit in the PMCiCOM0 register and bits EHOLD and SDEN in the PMC0COM0 register. Table
22.5 lists Conditions for Changing the REFLG Bit.
Table 22.5 Conditions for Changing the REFLG Bit
Bit Setting ⁽¹⁾
Conditions for Changing the REFLG Bit Conditions for Changing the REFLG bit
EHOLD HDEN
to 1 ⁽²⁾
to 0 ⁽²⁾⁽³⁾
0
0
Input signal width is neither data 0 nor Receive data 0 or data 1 (or special
data 1 (special data)
data)
0
1
• Input signal width is none of header, • Receive header
data 0, or data 1 (special data)
• Receive header prior to data 0 or data
• Detect data 0 or data 1 (or special
1 (or special data)
data) prior to header
1
0
Input signal width is neither data 0 nor -
data 1 (special data)
1
1
• Input signal width is none of header, • Receive header
data 0, or data 1 (special data)
• Detect data 0 or data1 (or special data)
prior to header
EHOLD: Bit in the PMC0COM0 register
HDEN: Bit in the PMCiCOM0 register (i = 0, 1)
Notes:
1. Refer to EHOLD = 0 when operating PMC1 individually.
2. Special data is added to the conditions when the SDEN bit in the PMC0COM0 register is 1
(special data enabled)
3. The REFLG bit becomes 0 regardless of bits HEDN and EHOLD under the following conditions:
•EN bit is 0 (PMCi stops)
•The DRFLG bit in the PMCiSTS register changes from 0 to 1 (next frame reception starts)
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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