M16C65 Datasheet, PDF (268/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
14. Interrupts
14.4 Software Interrupts
A software interrupt occurs when executing instructions. Software interrupts are non-maskable interrupts.
14.4.1 Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
14.4.2 Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag in the FLG register set
to 1 (the operation resulted in an overflow). The following are instructions whose O flag changes by an
arithmetic operation:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, and SUB
14.4.3 BRK Interrupt
A BRK interrupt occurs when the BRK instruction is executed.
14.4.4 INT Instruction Interrupt
An INT instruction interrupt occurs when the INT instruction is executed. Software interrupt numbers 0
to 63 can be specified for the INT instruction. Because software interrupt numbers 2 to 31, 41 to 51, 59,
and 60 are assigned to peripheral function interrupts, the same interrupt routine used for peripheral
function interrupts can be executed by executing the INT instruction.
For software interrupt numbers 0 to 31, the U flag is saved on the stack during instruction execution and
is cleared to 0 (ISP selected) before executing an interrupt sequence. The U flag is restored from the
stack when returning from the interrupt routine. For software interrupt numbers 32 to 63, the U flag does
not change state during instruction execution, and the SP selected at the time is used.
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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