M16C65 Datasheet, PDF (680/829 Pages) Renesas Technology Corp – RENESAS MCU M16C FAMILY / M16C/60

Under development
M16C/65 Group
Preliminary Specification
This is a preliminary specification and is subject to change.
26. Consumer Electronics Control (CEC) Function
Header block
CEC
ST
Set to 0 by a program
H7 H6
H1 H0 EOM ACK D7 D6
CTXDEN bit
CTFLG bit
Transmission starts at the rising
edge of the count source
Data block
D1 D0 EOM ACK
Set to 0 by
a program
CTD8FLG bit
IR bit in the
CEC1IC register
CCTB1 register
CCTBE bit
Rewritable period
by a program
0
CCTBA bit
Rewritable period
by a program
(Do not rewrite)
(Do not rewrite)
Undefined
CRXDEN bit
Set to 0 by acceptance of
an interrupt or by a program
Rewritable period
by a program
1
Rewritable period
by a program
(Do not rewrite)
(Do not rewrite)
Header block ACK
Rewritable period
by a program
Rewritable period
by a program
Data block ACK
CRFLG bit
CRSTFLG bit
CRD8FLG bit
IR bit in the
CEC2IC register
CCRB1 register
Set to 0 by acceptance of an
interrupt or by a program
Undefined
Set to 0 by acceptance of an
interrupt or by a program
Header block data
Data block data
CCRBE bit
CCRBAI bit
Undefined
Undefined
Header block EOM
Data block EOM
Header block ACK
Bits CTXDEN and CRXDEN: Bits in the CECC3 register
Bits CTFLG, CTD8FLG, CRFLG, CRD8FLG, and CRSTFLG: Bits in the CECFLG register
Bits CCTBE and CCTBA: Bits in the CCTB2 register
Bits CCRBE and CCRBAI: Bits in the CCRB2 register
Data block ACK
The above diagram applies under the following conditions:
y The CTISEL0 bit in the CISEL register is set to 1 (8th bit transmit interrupt enabled).
y The CTISEL1 bit in the CISEL register is set to 0 (10th bit transmit interrupt disabled).
y The CEMOM bit in the CECC3 register is set to 0 (EOM enabled).
y The CFIL bit in the CECC2 register is set to 0 (filter disabled).
y The CRISEL0 bit in the CISEL register is set to 0 (8th bit receive interrupt disabled).
y The CRISEL1 bit in the CISEL register is set to 1 (10th bit receive interrupt enabled).
y The CRISELS bit in the CISEL register is set to 1 (reception start bit interrupt enabled).
Figure 26.14 Transmission Example
REJ09B0484-0030 Rev.0.30 Sep 09, 2008
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